1. Field of the Invention
The present invention relates to a method of forming capacitor elements in an integrated circuit having a compound semiconductor substrate, and in particular to a method of forming highly miniaturized capacitor elements in an integrated circuit having a GaAs substrate on which are formed Schottky type field effect transistors (referred to in the following simply as FETs).
2. Description of the Related Art
FIGS. 1A and 1B are cross-sectional views to illustrate two prior art examples of configurations for a capacitor element which can be formed on a GaAs substrate of an integrated circuit. In FIG. 1A, an insulating film 4 functions as the dielectric layer of the capacitor element. The insulating film 4 also functions in general to provide electrical insulation between various connecting leads and electrodes of elements of the integrated circuit, these leads and electrodes having been formed by patterning processing of a single layer of a high-conductance material which is generally Au. For that reason, the insulating film 4 will be referred to as an inter-layer insulating film, to be distinguished from an insulating film portion which functions only as a dielectric layer of a capacitor element. In the manufacturing process for such a capacitor element (considering only the formation of a single capacitor element, for simplicity) a metallic film is formed overall on the main surface of the substrate by evaporative deposition and is then patterned to form a first electrically conducting film portion 2 which constitutes the lower electrode of the capacitor element. A film of electrically insulating material is then formed overall, and is patterned to form a through-hole therein for electrical connection to the first electrically conducting film portion 2. A film of a metal having high conductivity, e.g. Au, is then formed over the patterned electrically insulating film, and is patterned to define a second electrically conducting film portion 5 which lies directly over the first electrically conducting film portion 2 and constitutes the upper electrode of the capacitor element, and a third electrically conducting film portion 6 which is shaped to form a connecting lead for the first electrically conducting film portion 2 and is connected thereto via the through-hole in the electrically insulating film 4.
With the configuration of FIG. 1B, the dielectric layer of the capacitor element is formed of a different material (i.e. having a higher value of dielectric constant) from the inter-layer insulating film. In the manufacturing process for such a capacitor element, after first forming the first electrically conducting layer portion 2 as the lower electrode of the capacitor element, on the main surface of the GaAs substrate 1, an insulating film and a metallic layer are successively formed overall by evaporative deposition, then patterned by a photo-etching process to form an insulating film portion 4' as the dielectric layer of the capacitor element and a second electrically conducting film portion 5 as the upper electrode of the capacitor element. A film of electrically insulating material 9 is then formed overall, and is then patterned to form through-holes for connection to the first and second electrically conducting film portions 2 and 5. A metallic layer is then formed overall by evaporative deposition, and is patterned by etching to form a first connecting lead 5' which is coupled via a through-hole to the second electrically conducting film portion 5, and a second connecting lead 6 which is coupled via the other through-hole to the first electrically conducting film portion 2. A protective electrically insulating film 10 is then formed overall.
With a capacitor element having the configuration shown in FIG. 1A, the electrical properties required for an inter-layer insulating film of such an IC will be different from the optimum properties required for the dielectric layer of a capacitor element, and in particular the dielectric constant of the material used for the inter-layer insulating film will be insufficiently high. Hence in order to achieve a sufficiently high degree of capacitance for the capacitor element, it is necessary to make the thickness of the inter-layer insulating film extremely small. This leads to problems of low breakdown voltage levels and device failure.
In the case of a capacitor element having the configuration shown in FIG. 1B in which an electrically insulating film portion 4' is formed separately from the inter-layer insulating film 9, for use as the dielectric layer of the capacitor element, it becomes possible to select a material having a suitably high value of dielectric constant as the electrically insulating film portion 4'. However the problem then arises that it is necessary to perform a substantially greater number of manufacturing process steps than are required for the configuration of FIG. 1A, so that the manufacturing process becomes excessively complex.
However another problem arises with the configuration of FIG. 1B. In general, Au is used in the prior art as the material for the connecting leads 6, 5', and if that same material is also used to form the first electrically conducting film portion 2 as the lower electrode of the capacitor element, poor adherence will occur between the upper surface of that lower electrode and the electrically insulating film portion 4' if that electrically insulating film is formed of a material selected to obtain a high value of dielectric constant, and grain may be formed within the electrically insulating film. As a result it is found that the electrical insulation properties of the insulating film portion 4' are poor. Specifically, the breakdown electric field strength is low.